In many digital circuits, it is desirable to have a clock which will provide clock signals having two or more different frequencies, and these clock signals may also be synchronous with an external master clock. Many of these applications relate to circuits implemented with integrated circuits (ICs), Typical clock circuits of the prior art gate a clock driver with an enable signal which inhibits some of the positive-going (or negative-going) clock pulses. FIG. 1A illustrates a clock circuit 100 of the prior art providing two clock frequencies. As shown in FIG. 1A, an INPUT CLOCK signal and CLOCK ENABLE signal are provided to input terminals of AND gate 102 to provide an OUTPUT CLOCK signal. FIG. 1B is a timing diagram illustrating the operation of the clock circuit of FIG. 1A. For example, to divide the effective clock frequency by two, the CLOCK ENABLE signal inhibits every other positive-going clock pulse. However, the clock waveform of the OUTPUT CLOCK signal of such a circuit provides an asymmetric clock duty cycle. The asymmetry is of little concern in many applications; and if the pulse width provides sufficient propagation time for highest frequency of operation, it will be sufficient at lower frequencies as well.
Some circuit applications, such as analog circuits implemented on ICs, may be more sensitive to large asymmetries in duty cycle. In these applications, selection of different clock rates permits active tradeoff between speed and performance provided that the clock duty cycle remains balanced, or symmetric. For example, a data converter of an IC may be capable of higher resolution and/or lower power operation with low clock speed, provided the clock phases (and thus settling times) remain reasonably balanced. However, a symmetric clock circuit should be implemented with a simple circuit, similar to current clock driver circuits, to minimize complexity, power use, and IC real estate.
Therefore, there is a need for a clock driver circuit which is capable of buffering a master clock directly or generating a sub-harmonic clock with a balanced, or symmetric, duty-cycle. Furthermore, transitions between fast, slow, and disable modes of operation for such clock driver circuit should be glitchless and synchronous with a master clock signal.